There is a trend towards ever increasing complexity and ever greater miniaturization in the electronics industry. Space is at a premium, particularly in mobile equipment such as cellular phones and portable computers.
Integrated Circuits (ICs) are the heart of these electronic systems. As such, ICs are becoming more and more complex, and include ever larger numbers of transistors, and require increasing numbers of input/output contacts. They are required to operate at ever increasing switching speeds and frequencies, have ever increasing power consumptions and consequently generate ever increasing amounts of heat that requires dissipation.
ICs are connected to power supplies, user interfaces and other components via printed circuit boards (PCBs). To facilitate the connection of the IC to the PCB, it is necessary to provide a plurality of electronic connections. A common solution that has been adopted in order to interconnect the IC and its related PCB involves the usage of an Electronic Substrate. The Electronic Substrate is part of the IC package and replaces the traditional lead-frame as an interposer between the IC and the PCB. Such a substrate may include one, two or many conductor layers isolated by a variety of dielectric material layers, such as ceramic or organic materials. Such substrates generally have conductive arrays of contacts on their undersides. These may be ball contacts, providing a so called BGA (Ball Grid Array) or pins, providing a so-called PGA (Pin Grid Array) for electrical interconnection to the PCB. Alternatively, such substrates may be placed directly onto the PCB, without using balls or pins, providing a so-called LGA, (Land Grid Array) thereby. On its top side, the substrate will generally carry one or more ICs electrically connected thereto by the so-called Wire Bond or by the Flip Chip assembly techniques.
With reference to FIG. 1, an example of a Wire Bond BGA package of the prior art is shown, having a substrate 100; a ball grid array (BGA) of electrically conductive balls 102 that connects the pads 104 on the underside of the substrate 100 to a PCB therebeneath (not shown), and an array of electrically conductive wires, known as wire bonds 106, that connect the top side pads 108 of the substrate 100 to the IC 110. The IC 110 of such a package will usually be protected by a resinous material 112 that is otherwise known as a “molding” material.
With reference to FIG. 2, an example of a Flip Chip BGA package of the prior art is shown, having a Flip Chip BGA substrate 200. Once again, a ball grid array (BGA) 202 of electrically conductive balls is provided, that connects the pads 204 on the underside of the substrate 200 to the PCB therebeneath. Instead of wire bonds however, electrically conductive bumps 206 are provided on the top side pads 208 of the substrate 200, for connecting to the IC 210, by what is known in the art as the Flip Chip process. This process also involves the application of a resin material 212 between the IC 210 and the surface of the substrate 200. In this technology, the resin 212 is generally known as an “under-fill” material. The resin under-fill 212 acts as a stress buffer, and reduces the fatigue on the IC 210 and the bumps 206 during thermal cycling over the life time of the package 250. Sometimes the Flip Chip package 250 also includes a metal stiffener 216, which is attached to the substrate 200 by an adhesive layer 218, and a lid 220 that is attached to the back of the IC 210 with a thermal adhesive layer 222. The stiffener 216 is used to further stiffen the substrate 200 and helps maintain flatness during subsequent IC assembly processes, while the lid 220 helps dissipate the heat generated by the IC 210 during its operation.
The advanced BGA, PGA, LGA substrates used in Wire Bond and Flip Chip processes described hereabove and illustrated in FIGS. 1 and 2 respectively, generally include two main sections: a so-called “core section” and a “built-up section” that is applied layer by layer thereupon.
With reference to FIG. 3, a detailed example of a typical organic Flip Chip BGA (FCBGA) substrate 300 is shown. The core section 330 of the substrate 300 is constructed out of multiple copper conductor layers 332 that are usually separated by fiber-glass reinforced, organic dielectric material layers 334. The copper conductor layers 332 in the core 330 are electrically connected by Plated Through Holes (henceforth PTH) 336. Generally, in the process of forming the substrate 300, the core section 330 is formed first. PTHs 336 are then formed by mechanically drilling holes, copper plating them and plugging. Next, external copper conductor layers 338 of the core section 330 are constructed. Two built-up sections 340′, 340″ are then added, one on each side of the core 300. These built-up sections 340′, 340″ consist of a plurality of conductor copper layers 342, separated from each other by layers 344 of dielectric material, which may be reinforced by fiber-glass. The dielectric layers 344 contain copper plated micro-vias 346, which interconnect between adjacent copper conductor layers. The micro-vias 346 are usually laser drilled and hence are much smaller in diameter than the PTHs 336. This releases valuable space on the substrate's built up sections for applying ICs thereupon. The improved mechanical and electrical characteristics of the dielectrics used in the built-up sections, together with their higher conductor densities, enabled by the usage of the micro-vias 346, allow them, eventually, to reach the density of the IC contacts and to act as intermediating contacts to the PCB.
It will be noted that the core section 330 of such an FCBGA substrate 300 primarily serves as a through interconnect “carrier” for the build-up sections 340′, 340″, whilst also accommodating the low density power and ground copper conductor layers required to operate the IC.
Due to their finer I/O pitches, modern ICs require very flat, non-warped substrates to ensure the reliability of the package. This is difficult to achieve if the built-up section of the substrate is only formed on one side of the core. In order to create a flat, non-warped substrate during IC assembly processes and thereafter, the built-up sections are preferably built up on both sides of the core, so that a symmetrical structure is fabricated, resulting in a stress-balanced, flat substrate.
There is a cost to building up layers on both sides of the core however. It adds more manufacturing process steps, which, in turn, increases fabrication costs. Since the resulting substrate structure is more complicated, manufacturing yields drop off. Furthermore, the substrate thickness is increased, resulting in less compact, thicker packages that are less desirable for mobile communication and other applications where miniaturization is required. Additionally, it will be appreciated that the thicker the substrate, the greater the total inductance and thermal impedance of the package. This deteriorates the over all performance of the IC. In view of these drawbacks, many attempts have been made to improve on the sandwich structure described above.
One development that attempts to minimize thickness is to construct the substrate without a central core, providing what is known in the art as a “core-less substrate”. In this concept, both the central core and the build-up section from the substrate's BGA (or PGA or LGA) side are eliminated, so that the entire substrate consists of one build-up section only, for interconnecting the IC to the PCB. The total substrate thickness is thereby significantly reduced, improving both its thermal impedance and its electrical performance. Furthermore, eliminating the core section of the substrate cuts down the cycle time of the manufacturing process and eliminates the need for mechanically drilled PTHs which are fairly expensive to fabricate.
United States Published Patent Application Number USSN 2002/0001937 to Kikuchi et al. addresses the above issues by describing the manufacturing of multilayer interconnect structures consisting of polymeric insulating layers and metal interconnects on a metal base plate that is subsequently partially removed to create a metal supporting stiffener having an aperture for the IC.
While USSN 2002/0001937 to Kikuchi et al apparently introduces a viable methodology for obtaining a core-less substrate, it nevertheless suffers from a number of drawbacks. Firstly, all the conductor layers of the substrate require expensive thin film interconnects. While conductor layers in the form of thin film interconnects provide better performance due to their improved densities and finer pitches, they are inappropriate to the substrate's power and ground metal planes which are usually low in density and pitch, and building them using expensive thin film technology is cost prohibitive. Furthermore, these layers usually require a certain metal thickness to reduce electrical resistance and to prevent overheating. This can become difficult to achieve when using thin film processing techniques. Furthermore, the Flip Chip bonding process applies a pressure which thin film interconnect structures are ill equipped to withstand. Such pressures tend to distort and/or stretch the interconnect structure, which in thin films are typically less than 100 microns thick. This sometimes causes cracking of the thin film dielectric layers and may lead to operating failure of the IC. Additionally, it will be appreciated that the presence of a metal stiffener adjacent to the IC consumes valuable space on the external surface of the substrate and may limit usage in applications requiring passive components, such as decoupling capacitors, in close proximity to the IC. Furthermore, the large aperture metal stiffener used may make this technology unsuitable for applications requiring, for example, multi chip substrates, low body-sized substrates, substrates supplied in two dimensional matrix arrays or in strip formats.
U.S. Pat. No. 6,872,589 to Strandberg describes a substrate for mounting an IC. Here again, the substrate structure is formed on a metal carrier base which is only partially etched away, leaving a metal stiffener having an aperture for the mounted IC. Although Strandberg's substrate described in U.S. Pat. No. 6,872,589 may be advantageous over that described in USSN 2002/0001937 by offering a lower interconnect layer count, it nevertheless still suffers from all the drawbacks of the structure of USSN 2002/0001937 as detailed above.
In light of the above it is clear that there is still a need for cost-effective, higher performance core-less substrates that can be used in a wide range of applications. To satisfy this need, one promising approach has been to attempt to eliminate the expensive thin film build-up structures described above and to replace them with other, cheaper materials and processes such as those established by and in common use in the printed circuit board (PCB) fabrication industry. Unlike thin film dielectric materials, the advanced dielectric materials used in the PCB industry may be applied by lamination techniques and are available in the form of prepregs which may be reinforced with glass fibers or other reinforcement materials. Proper selection of these dielectrics provides the potential to introduce “self supported” core-less substrate structures that eliminate or at least minimize the need for metal stiffeners. Furthermore, use of relatively low cost, established, PCB oriented processes, is expected to provide cost effective core-less substrates having multiple, low density, low pitch power and ground metal layers combined with high density, fine pitch metal signal layers.
Such laminate structures have been found to be susceptible to warping, particularly in consequence of hot pressing or curing processes. Core-less substrates obtained thereby, typically lack the flatness required for securely and reliably mounting ICs thereupon.
Where such substrates have been built up on one side of a metal carrier base that is subsequently removed prior to IC assembly, or thinned down to provide a stiffener supported substrate, internal unbalanced stresses invariably develop during fabrication. These stresses may be released on removal of the metal carrier, causing substrate curvature and warping. This can result in poor yields when assembling the IC thereupon, and may even lead to non flat packages that cannot then be mounted onto the corresponding PCB.
In an attempt to solve this issue, U.S. Pat. No. 6,913,814 to Ho et al. discloses a lamination process and resultant structure that provides a high density multi-layer substrate having a plurality of laminate layers, wherein each layer thereof is individually formed, and, only then are the layers stacked and laminated together. This approach apparently provides a viable alternative to the asymmetrical, sequentially built up, multi-layer substrates fabricated on a common metal carrier base of the prior art. The technology seems to provide a cost effective organic core-less substrate using tried and tested materials and processes established by the PCB fabrication industry, with solid copper vias replacing the PTHs.
Nevertheless, the technology described in U.S. Pat. No. 6,913,814 to Ho et al. has two major drawbacks: Firstly, in order to construct a structure having a bottom layer with a low pitch BGA thereupon for attachment to a PCB and a high pitch upper IC side, the substrate must be constructed from individual laminae, each having different densities and different dielectric layer thicknesses. Once again this results in an unbalanced, asymmetrical, structure with an inherent tendency to curving. Secondly, as is well known to those experienced in the art, connecting the substrate layers with via-to-pad contacts based upon metal contacts achieved through dielectric materials lamination is unreliable for high performance ICs applications, since these have a tendency towards loss of via contact and resultant package failures. This is especially of concern where high temperature processes are used during IC mounting onto the substrate.
In a co-pending application to the present inventors, IL 171378 filed 11 Oct. 2005 to Hurwitz et al., entitled “Novel Integrated Circuit Support Structures and their Fabrication” a method of fabricating an electronic substrate is described that addresses this issue. The fabrication method comprises the steps of: (a) selecting a first base layer; (b) applying a first etchant resistant barrier layer onto the first base layer; (c) applying a seed layer of copper; (d) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (e) applying a second metal base layer onto the first half stack; (f) applying a protective coating of photoresist to the second base layer; (g) etching away the first base layer; (h) removing photoresist; (I) removing the first etchant resistant barrier layer; (j) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein second half stack has a substantially symmetrical lay up to first half stack; (k) applying an insulating layer onto the second half stack of alternating conductive layers and insulating layers, and (l) removing the second base layer.
The processing method of IL 171378 to Hurwitz et al., essentially consists of building up half the desired structure on a sacrificial substrate, terminating the half structure stack with a thick layer that becomes a second sacrificial substrate, removing the first sacrificial substrate and building down a second half structure stack that is substantially symmetrical to the first half structure stack. Thus the first layers to be applied become the middle layers of the stack.
In theory, the first and second half structure stacks are mirror images of each other and have opposite residual stresses that cancel each other out giving a planar structure that shows no tendency to warp. However, because the stack is fabricated from the center outwards, with one half stack being fabricated first, from the center outwards, followed by the second half stack being fabricated on the first half stack, again from the center outwards, it is difficult to ensure that the processing conditions remain the same for the two half stacks, especially for structures with large numbers of layers. Discrepancies between the two sides typically results in some unbalanced residual stresses in the substrate that may lead to warping, resulting in the substrates that do not reach the strict planarity requirements of advanced IC package constructions, such as Package on Package (PoP), Package in Package (PiP), packages containing stacked ICs, and packages containing several ICs mounted by flip chip processes and others by Wire Bond techniques. For this and other reasons, the processing method of co-pending IL 171378 to Hurwitz et al., though being a major step forward in the art, nevertheless has limited applicability for very complicated, multilayered structures having a large number of active layers, and attempts to fabricate such structures have, in the past, lead to reduced yields.
Thus, despite the developments described above, and the major advantages of IL 171378 to Hurwitz, with regards to reliability due to high levels of planarity and smoothness, there is still a need for quick turnaround manufacturing processes and for chip support structures that are economical to manufacture and give high yields even for high count multilayer structures. The present invention addresses this need and presents new processing techniques and novel structures.